1. Technical Field
The present invention relates to a semiconductor memory device, and more particularly, to a sense amplifier, a semiconductor memory device including the sense amplifier, and a data sensing method.
2. Discussion of the Related Art
In a semiconductor memory device including a dynamic random access memory (DRAM), data stored in a memory cell is read by a sense amplifier connected to a bit line. The data stored in the memory cell is transferred to the sense amplifier through the bit line, amplified by the sense amplifier, and then output from the sense amplifier. In this manner, the data stored in the memory cell is read.
Bit lines and sense amplifiers are generally arranged according to a folded bit line structure or an open bit line structure. In the folded bit line structure, two bit lines in a pair are connected to the same memory cell array. In the open bit line structure, the two bit lines in a pair are respectively connected to different memory cell arrays.
FIG. 1 is a block diagram of a conventional semiconductor memory device 100 including a plurality of memory cell arrays 110-1, 110-2, . . . and a plurality of sense amplifiers 130-1, 130-2, . . . . FIG. 2 is diagram explaining the folded bit line structure. FIG. 3 is a diagram explaining the open bit line structure.
Referring to FIG. 1, in the semiconductor memory device 100, the plurality of memory cell arrays 110-1, 110-2, . . . and the plurality of sense amplifiers 130-1, 130-2, . . . are arranged in an alternating pattern 150. It will be understood by those of ordinary skill in the art that the memory cell arrays can be either blocks or banks.
Referring to FIG. 2, bit line pairs BL0 and /BL0, BL1 and /BL1, through BLN and /BLN are respectively connected to the memory cell arrays 110-1, 110-2, . . . in the folded bit line structure. Thus, the number of the memory cell arrays is equal to the number of the sense amplifiers in the semiconductor memory device 100.
Referring to FIG. 3, two bit lines in a pair, BL0 and /BL0, BL1 and /BL1, through BLN and /BLN, are respectively connected to neighboring memory cell arrays 110-1 and 110-2, for example, in the open bit line structure. Thus, the number of the memory cell arrays of the semiconductor memory device 100 is greater than the number of the sense amplifiers by one. A semiconductor memory device therefore requires one more memory cell array when it employs the open bit line structure compared to when it employs the folded bit line structure.
With the advancement of semiconductor memory device technology, the chip size of a semiconductor memory device is reduced and a process for designing the semiconductor memory device becomes more delicate. Accordingly, a bit line pitch becomes important in the design of a region where bit lines and sense amplifiers are arranged.
It can be seen from FIGS. 2 and 3 that the open bit line structure has a more desirable bit line pitch than the folded bit line structure. Thus, the open bit line structure is widely used to design a region where bit lines and sense amplifiers are arranged in the current semiconductor memory device.
However, as illustrated in FIG. 3, in the open bit line structure, as many as half the bit lines arranged in the outmost memory cell array are DUMMY hit lines and are not used in the semiconductor memory device 100. Thus, memory cells connected to the DUMMY bit lines become dummy cells that are not used.
In the case of the semiconductor memory device 100 illustrated in FIG. 3, when dummy cells of the rightmost memory cell array and the leftmost memory cell arrays are considered, memory cells corresponding to a single memory cell array are not used. Accordingly, the open bit line structure brings about large loss in the area and increased cost of a semiconductor memory device.